Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1

[Marko Mlinar <markom@opencores.org>]

On Wednesday 28 May 2003 15:04, Tom Hawkins wrote:
> On Tuesday 27 May 2003 10:29 pm, Rudolf Usselmann wrote:
> > On Wed, 2003-05-28 at 02:20, Tom Hawkins wrote:
> > > On Tuesday 27 May 2003 11:58 am, Shehryar Shaheen wrote:
> > > > So what would Sytem Verilog have in the offing that
> > > >  SystemC doesn't ?
> > > >
> > > > Would you think that the reason that SystemC is not popular is
> > > >  cause the learning curve associated with a new language tends
> > > >  to put off many users who already have a firm grip over
> > > > current HDLs ?
> > >
> > > SystemC is not popular because C, object-orientation, and
> > > imperative programming are very poor languages and paradigms for
> > > describing hardware systems.
> >
> > I have to disagree here, Tom. It's not the Object Oriented aspect
> > that make a language like SystemC dis-liked by most HW designers.
> > Matter of fact, Object Oriented languages are quite popular, look
> > at Vera and E.
>
> Rudi, I agree with you here.  OO works well in the test bench.  But
> for synthesizable RTL, how often you you code a StateMachine class
> that inherits from BaseStateMachine and extend the Reset and
> StateTransistion methods?

Tom,

don't underestimate OO for synthesis. Although OO may seem unsuitable for RTL 
at first glance, but as a user of OO RTL language (for synthesis!) I can say 
with much confidence, that it is useful at least for:
- memory block, different vendors, etc...
- pads
- cores
- interfaces
...

The OO defines an abstraction in different way than just defining 'interface' 
module as it is currently done in Verilog. For example you may define 
wishbone interface:

wire[31:0] x = wishbone.read(address);

where 'read' is a part of bus interface interface.

As you can see you have numerous posibilities to exploit OO, the problem is 
just that HW enginners are not used to this way of thinking or even worse -- 
they don't understand it and therefore they declare it as 'useless' toy for 
SW guys ;)

unfortunately I don't think SystemVerilog will have support for synthesisable 
functions as it is done in the above case.

best regads,
Marko


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