Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1

[John Sheahan <jrsheahan@optushome.com.au>]

On Thu, May 29, 2003 at 10:26:48PM +0100, Shehryar Shaheen wrote:
> 
> > Is there any quickly way to code a netlist given a
> > handful of components without having to worry about execution order?
> 
> All declared concurent processes will execute in parallel much like all
> always blocks
>  in verilog execute in parallel and all processes in VHDL.

you appear to have ducked this question. Instantiations and assigns 
are parallel too, and are short and clear.
john
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