[cvs-checkins] ethernet/rtl/verilog eth_clockgen.v eth_crc.v ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	ethernet
Changes by:	mohor	01/08/06 16:44:29

Added files:
	rtl/verilog    : eth_clockgen.v eth_crc.v eth_defines.v 
	                 eth_maccontrol.v eth_macstatus.v eth_miim.v 
	                 eth_outputcontrol.v eth_random.v 
	                 eth_receivecontrol.v eth_register.v 
	                 eth_registers.v eth_rxcounters.v eth_rxethmac.v 
	                 eth_rxstatem.v eth_shiftreg.v eth_timescale.v 
	                 eth_top.v eth_transmitcontrol.v 
	                 eth_txcounters.v eth_txethmac.v eth_txstatem.v 
	                 eth_wishbonedma.v 
Removed files:
	rtl/verilog    : clockgen.v counters.v crc.v ethdefines.v 
	                 ethernettop.v ethregisters.v maccontrol.v 
	                 macstatus.v miim.v outputcontrol.v random.v 
	                 receivecontrol.v rxcounters.v rxethmac.v 
	                 rxstatem.v shiftreg.v statem.v 
	                 transmitcontrol.v txethmac.v wishbonedma.v 

Log message:
	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
	Include files fixed to contain no path.
	File names and module names changed ta have a eth_ prologue in the name.
	File eth_timescale.v is used to define timescale
	All pin names on the top module are changed to contain _I, _O or _OE at the end.
	Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
	and Mdo_OE. The bidirectional signal must be created on the top level. This
	is done due to the ASIC tools.

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