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[cvs-checkins] wb_dma/ tl/verilog/wb_dma_ch_pri_enc.v im/rtl_ ...

CVSROOT:	/home/oc/cvs
Module name:	wb_dma
Changes by:	rudi	01/08/07 10:00:45

Modified files:
	rtl/verilog    : wb_dma_ch_pri_enc.v 
	sim/rtl_sim/bin: Makefile 
	syn/bin        : design_spec.dc 
Added files:
	rtl/verilog    : wb_dma_pri_enc_sub.v 

Log message:
	Split up priority encoder modules to separate files

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