[cvs-checkins] uart16550/rtl/verilog uart_regs.v

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	mohor	01/12/12 10:05:50

Modified files:
	rtl/verilog    : uart_regs.v 

Log message:
	LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).

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