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[cvs-checkins] uart16550/rtl/verilog uart_regs.v

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] uart16550/rtl/verilog uart_regs.v
From: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
Date: Thu, 13 Dec 2001 11:09:17 +0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	mohor	01/12/13 11:09:17

Modified files:
	rtl/verilog    : uart_regs.v 

Log message:
	thre irq should be cleared only when being source of interrupt.

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