RE: [ethmac] Ethernet MAC host interface

[Gavin Hurlbut <gjhurlbu@beirdo.ott.uplink.on.ca>]

Just a little update...

I have written a VHDL module to interface a generic 32-bit wide Wishbone bus
to the 32-bit-only Wishbone bus interface on the Ethernet MAC. It effectively
combines the multiple Wishbone writes into a single write with all 32-bits
of data, and does the same for reads.  I'm glad I did it separately as there
are other cores I'm using that also require Wishbone bus access combining.

This allows me to interface my 8-bit host bus (through bus resizers, etc) to
the ethernet MAC core.  I have simulated this successfully (using Xilinx
Foundation 3.1i) and have even managed to get the Verilog cores to play well
with my VHDL cores (using EDIF files, and black-boxing the Verilog cores).

If anyone is interested in getting my wishbone bus access combiner from me, I
would be happy to pass it on.  It requires the use of the wb_tk stuff from
opencores at this time, and I may offer it to that project for inclusion if
they are interested.

Adios.
Gavin

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