RE: [ethmac] Ethernet MAC host interface

["Igor Mohor (uni-mb)" <igor.mohor@uni-mb.si>]

Hi, Gavin,

If you want to use WISHBONE interface, you have to be able to generate
32-bit accesses. This decision was made by several developers to simplify
the logic. I your case the word "simplify" might not be appropriate :)

The other way is to make your own interface (that will work with yourhost).

Regards,
	Igor


> -----Original Message-----
> From: owner-ethmac@opencores.org [mailto:owner-ethmac@opencores.org]On
> Behalf Of Gavin Hurlbut
> Sent: 09. september 2001 6:29
> To: ethmac@opencores.org
> Subject: [ethmac] Ethernet MAC host interface
>
>
> Hello.  I am just starting to reimplement large chunks of a home
> project FPGA
> I am doing, and I am attempting to replace my hand-done 10/100
> MAC with the
> one from OpenCores.org as this seemed like the right thing to do,
> and I hadn't
> gotten far yet anyways.
>
> Anyways, I notice that your host interface is a Wishbone bus
> (which I think is
> a grand idea!), but that you have several limitations on its use
> that will make
> life difficult in my project.  I thought that before I go and
> hack the core
> to fit my uses, I'd bring it up in the mailing list to see what
> reaction there
> is...  BTW, I would be more than happy to submit my changes once
> I'm done.. :)
>
> My project uses an external 8051 derivative chip, and I am
> attempting to do all
> my FPGA stuff around a Wishbone bus with a 32-bit width to allow
> for better
> efficiency.  However, this poses several small problems.
>
>
> a)  I will never be generating 32-bit accesses unless I implement
> some funky
> bus access consoldation core that will bring the accesses into one...
>
> b)  I don't have a 32-bit address bus anywhere.  Internally, I
> have a 17-bit
> address bus (14 bits + 3 selects), with the MSB being driven from PSEN to
> indicate code accesses.  Lovely Harvard architecture...  I was
> expecting to use
> an internal address decoder, and multiplexed data bus internally,
> and to have
> my cores using a partial address decoding technique (see p72 of
> the Wishbone
> Spec, rev B).  The current ethernet MAC core expects to do a full address
> decoding.
>
> c)  The core is done in Verilog, and I'm a VHDL guy.  I hope I can get my
> Xilinx tools to behave with mixed HDL input. :)
>
> So I'm intending to change the host interface to deal with
> problem b).  How to
> deal with a) above is up for discussion.
>
> Any ideas before I go and hack this core?  :)
>
> Ciao
> Gavin
>
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