RE: [ethmac] ethernet core information

["Igor Mohor (uni-mb)" <igor.mohor@uni-mb.si>]

Hi, Rodrigo,

I don't know how you intend to serve and accept data to/from ethernet MAC.
Whatever you will use for that manner, the easiest way to do it is to build
something that is WISHBONE compatible. Read the standard from the opencores
webpage. It is not complicatedat all.

There is no VHDL ethernet core.

Regards,
	Igor

> -----Original Message-----
> From: owner-ethmac@opencores.org [mailto:owner-ethmac@opencores.org]On
> Behalf Of Rodrigo Sosa
> Sent: 20. september 2001 16:15
> To: ethmac@opencores.org_NOSPAM; ethmac@opencores.org
> Subject: [ethmac] ethernet core information
>
>
> Hi!,
> I'm writing to you because I´m trying to implement the ethernet
> core into an
> FPGA.
> I have a board with a Virtex FPGA and a Ethernet Phy Transceiver.
>
> I have read the ip core document, but there is something that i'm
> not used
> to.
> The wishbone interface......
> Should I have and extra module to control the ip core, or it should work
> like an stand alone design?
>
> Maybe it  is a silly question,  but I just want to know if I have
> to design
> a kind of control module compatible with the wishbone interface.
>
> Do you have something developed (ethernet cores) in VHDL ?
>
>
> Thank you
>
> =================OOOO====================
>
>           Rodrigo Sosa Lopez
>    Universidad de las Americas Puebla
>     Ing. Electronica y Comunicaciones
>   e-mail: sosa_rodrigo@hotmail.com
>
>
>
>
> _________________________________________________________________
> Get your FREE download of MSN Explorer at http://explorer.msn.com/intl.asp
>
> --
> To unsubscribe from ethmac mailing list please visit
http://www.opencores.org/mailinglists.shtml

--
To unsubscribe from ethmac mailing list please visit http://www.opencores.org/mailinglists.shtml