RE: [ethmac] Some silly questions

["Igor Mohor (uni-mb)" <igor.mohor@uni-mb.si>]

Hi, Erez,

Sorry, I was out of the internet reach these days.



> -----Original Message-----
> From: owner-ethmac@opencores.org [mailto:owner-ethmac@opencores.org]On
> Behalf Of Erez Volk
> Sent: 21. september 2001 17:32
> To: ethmac mailing list
> Subject: [ethmac] Some silly questions
>
>
> Hello everyone
>
> I am adding a simulation of the ethernet MAC to the OpenRisc simulator,
> and after reading the specs (Eth_spec.pdf) I have some questions:
>
> 1. Just to make sure: In the table describing the registers and their
> addresses, addresses go 0x00, 0x01, 0x02... -- shouldn't that be in
> multiples of 4, e.g. 0x00, 0x04, 0x08...?
>

If you're talking about address from the wishbone point of view, than you're
correct. I'll change that in the documentation. I was busy lately and didn't
have time to update the documentation. Sorry.


> 2. I see the definitions of registers TX_STATUS0..TX_STATUSn and
> RX_STATUS0..RX_STATUSn: So what is n?  Is it 255?  And what exactly is
> "frame 0/1/whatever"?  I mean, say the RISC transmits 3 frames (using a
> linked list etc.) -- are they then TX_STATUS0..2, and after the next
> transmition this is overwritten etc.?  And what about receiving?
>

The documentation doesn't 100 % reflect the state of the hardware. Sorry,
lack
of time. I'll do my best to finish that really soon. Forget about those
registers. They're not used any more. Status is now written to the memory
through the Wishbone.

> 3. Are the values for the status registers defined yet?
>

I already answered to thih question also. Give me few days for the update.

> Thanks,
> Erez

Regards,
	Igor


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