RE: [ethmac] Gigabit Ethernet controller

[Illan Glasner <IGlasner@mrv.com>]

Hi,

   I belive couple of years ago I interfaced with the m8101 and as far as I
can recall it basicly had a 32 bit data bus 4 bit be, sof, eof and fct bus
for signaling ready.

as for testing methology mine is similar regadless of the project meaning I
get all the verilog module of the component I use (if possibale) as well as
write sort of dummy component to enbale faser simulation and than simulate
the whole system.

in the Gig case for example assuming your fpga interface in one side with
let say cpu and the other side with this Gig Core and the Gig core is than
hocked to a Gig Phy, I will than write a dummy Gig phy and dummy cpu and
than send packet from the cpu to the gig phy and vice versa and while
generating the packet I will also generate expected and when I get packet I
will print them as well and at the end once the simulation is done using
unix script I will compare what I expect with what I got.
of course if your fpga also need to be initilize or the Gig core through a
cpu interface you should make sure the dummy cpu also write all those
initilize trasaction before the packet are enjected to the system.

have a nice day

   Illan

-----Original Message-----
From: pushpamurali006@yahoo.com [mailto:pushpamurali006@yahoo.com]
Sent: Wednesday, September 04, 2002 7:56 AM
To: ethmac@opencores.org
Subject: [ethmac] Gigabit Ethernet controller


Hai,
I am Pushpa from Bangalore.
I would like to know if any one has worked with L8101 Gigabit Ethernet 
Controller?If so can u please tell the testing methodology?
I would like to know the handshakng between FPGA and MAC.

With regards,
pushpa
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