RE: [ethmac] Burst Writes/Reads on the Wishbone

["Igor Mohor" <igorm@opencores.org>]

Hi.

Look at the figures 4-3 and 4-4 and you'll get the answer.

Regards,
	Igor

> -----Original Message-----
> From: owner-ethmac@opencores.org [mailto:owner-ethmac@opencores.org]On
> Behalf Of Lake, Matt A @ PWC
> Sent: 24. oktober 2002 22:16
> To: 'ethmac@opencores.org'
> Subject: [ethmac] Burst Writes/Reads on the Wishbone
>
>
> While testing the design of the ethmac i noticed something that
> troubled me.
> After i have buffered a packet into off-chip SRAM i do a write
> the MAC BD to
> tell it there is a Packet in memory for it to transmit.  Then the
> MAC comes
> out to memory using it's wishbone compatible interface and begins to do a
> "burst" read from the memory to fill it's internal fifo with the
> data to be
> transmited.  Well that is fine execpt it doesn't look to me like the MAC
> memory wishbone signals are really wishbone compatible.  It asserts
> m_wb_cyc_o and m_wb_stb_o as well as the address it wants to read from.  I
> then give the MAC it's data and the apropriate acknowlege.  This is where
> the problem occurs.  According to the wishbone spec on page 51 (Block
> Read/Write Cycles) it says that m_wb_cyc_o will stay high during
> the entire
> block read/write, which it does in simulation, and then it says that
> m_wb_stb_o will cycle with each access in a block read/write,
> i.e. it should
> be asserted high then deassert when an acknowlege is given then it will
> reassert m_wb_stb_o with each subsequent access in the block read/write.
> Well in simulation the m_wb_stb_o signal stays high during the
> entire block
> read/write.  The MAC will put out a new address when it recieves the
> acknowledge but it leaves both m_wb_stb_o and m_wb_cyc_o high the entire
> time.  I dont think this is the correct operation.  Can anyone
> tell me if im
> correct in beliveing that what i am seeing in simulation is not
> correct for
> a wishbone compliant block read/write.  Thank you all for your time.
>
> _____________________________________________
> Matt Lake
>
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