Re: [ethmac] Burst Writes/Reads on the Wishbone

[NICHOLAS DAVID LINDBERG <ndlindberg@students.wisc.edu>]

Matt,

Do you have verilog code written for reading and writing buffer 
descriptors?  I'm trying to basically do the same thing you are for a 
class project but I can't figure out how the MAC is supposed to know 
what address to write the memory to once it gets data from the PHY.  
Does the mac keep track of memory mapping?  And how does it know which 
buffer descriptors (or how do I konw which buffer descriptors to 
read/write when I want to transmit/send data in the 0x800-0xfff memory 
space?)  

One last thing: let me know if this sounds right as far as operation 
goes:
1) write to all the appropriate status registers to initialize the MAC
2) turn on the Rx and Tx by setting RxEnable bit and TxEnable bit to 1.
3) now it's ready to go (I can start writing Tx buffer descriptors and 
reading Rx buffer descriptors when an interrupt is issued)

Thanks,
Nick

----- Original Message -----
From: "Lake, Matt A @ PWC" <matt.a.lake@l-3com.com>
Date: Thursday, October 24, 2002 3:15 pm
Subject: [ethmac] Burst Writes/Reads on the Wishbone

> While testing the design of the ethmac i noticed something that 
> troubled me.
> After i have buffered a packet into off-chip SRAM i do a write the 
> MAC BD to
> tell it there is a Packet in memory for it to transmit.  Then the 
> MAC comes
> out to memory using it's wishbone compatible interface and begins 
> to do a
> "burst" read from the memory to fill it's internal fifo with the 
> data to be
> transmited.  Well that is fine execpt it doesn't look to me like 
> the MAC
> memory wishbone signals are really wishbone compatible.  It asserts
> m_wb_cyc_o and m_wb_stb_o as well as the address it wants to read 
> from.  I
> then give the MAC it's data and the apropriate acknowlege.  This 
> is where
> the problem occurs.  According to the wishbone spec on page 51 (Block
> Read/Write Cycles) it says that m_wb_cyc_o will stay high during 
> the entire
> block read/write, which it does in simulation, and then it says that
> m_wb_stb_o will cycle with each access in a block read/write, i.e. 
> it should
> be asserted high then deassert when an acknowlege is given then it 
> willreassert m_wb_stb_o with each subsequent access in the block 
> read/write.Well in simulation the m_wb_stb_o signal stays high 
> during the entire block
> read/write.  The MAC will put out a new address when it recieves the
> acknowledge but it leaves both m_wb_stb_o and m_wb_cyc_o high the 
> entiretime.  I dont think this is the correct operation.  Can 
> anyone tell me if im
> correct in beliveing that what i am seeing in simulation is not 
> correct for
> a wishbone compliant block read/write.  Thank you all for your time.
> 
> _____________________________________________
> Matt Lake
> 
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