[openrisc] Re: [bender] Comments on the interrupt controller...

["Damjan Lampret" <lampret@opencores.org>]

Chris,

we can change SR[EXR], SR[EIR] and related stuff but only if you promise
that you'll help to close architecture in a week. People want RTL, you want
to change fundamental things in architecture and result is that I'm geting
paranoid because gap between architecture, tools (or1ksim in this case) and
OR1200 is getting wider and not narrower. For example Greg McGary who is now
helping Johan with some issue on tools, he proposed additional features to
the architecture. Even though these are just features and not mandatory
changes, he'd like to see them added (add he knows what he is proposing
since he just finished complete GNU toolchain for a proprietary RISC
processor from RedBack Networks).

So if you think four exceptions that you listed really shoudln't be masked,
then we can change it. But I wrote exception handlers for PowerPC and I know
there is no problem with our approach which is in exception area very
similar to PPC.

Anyway I think this topic should move to openrisc mailing list.

regards,
Damjan