[openrisc] closing OR1K architecture soon

["Damjan Lampret" <lampret@opencores.org>]

Hi everyone,

I hope we can finally close OR1K architecture (hopefully in a week). So
please have a look at current architecture manual and send comments to
openrisc mailing list. Current manual is available at
http://www.opencores.org/cgi-bin/cvsget.cgi/or1k/docs/openrisc_arch3.pdf
(2.5MB)

Currently these architectural changes are scheduled to be done in a very
near future:
- Chris & Matan's proposal for exception prefix (ie. where in address space
exception handlers are located). Currently idea is to add a bit in SR that
selects between two predefined memory areas.
- Matan's suggestion for having small TLB for large pages since current
scheme can't handle them properly.
- Chris's suggestion for test and set atomic instruction (or swap
instruction) instead of current atomic instruction pair.
- Greg's conditional move reg->reg
- Greg's conditional trap instructions (like teq etc in MIPS)

After these changes are in the architecture manual, I'll update OR1200 spec
(http://www.opencores.org/cgi-bin/cvsget.cgi/or1k/docs/openrisc1200_spec.pdf
(2.5MB)) and publish compliant OR1200 RTL code.

If there are volunteers to help Matan with Linux port, Chris with RTEMS port
or Johan with eCos port, please respond to the list. Also if you want to
verify or1ksim and GNU toolchain, please respond to the list.

regards,
Damjan

PS I think it is good to set a date for closing OR1K architecture (at least
parts of it relevant to OR1200 implementation - meaning ORFPX64 and ORVDX
can be changed in the future). I think May 15 is a good date.