[openrisc] Address pipeline during exception...

[Chris Ziomkowski <chris@asics.ws>]

 The architectural simulator currently does not simulate
an ic_mmu_fetch for exceptions.

This may be completely acceptable, as the mmu is
disabled during exceptions, however, the pc_phy
register is not set at all, and this causes the simulator
to crash. I have fixed this in the file

cpu/or1k/except.c

by simply setting pc_phy to pc.

This raises the more interesting question though of
what does happen during an exception. The Or1k
manual does not state how many cycles it takes for
an exception to be processed. I'm guessing 2
because it must reload the instruction pipeline. Is this
correct?

The simulator needs to be modified to account for
this, because other peripherals, such as the serial
port, are still executing and the timing between them
needs to be correct.

I've added a cycle_delay register that is set whenever
an exception occurs and is processed by toplevel.c to
ignore the cpu unit but update all the peripherals to
accomodate this condition.

Comments?

Chris
chris@asics.ws