Re: [openrisc] how to debug memory and cache controller

[sivaiit@yahoo.com]

----- Original Message ----- 
From: "ssy" <skli@n... > 
To: <openrisc@o... > 
Date: Sat, 9 Jun 2001 10:17:19 +0800 
Subject: [openrisc] how to debug memory and cache controller 

> 
 
 
 
> Hi dear or1k developer:
 
>  
 
> I want to ask a question to you, when i declare a memory block 
 as 
> follow:
 
> reg [7:0] memory [255:0];
 
> in cache controller,How can I view its value.
 
>  
 
> I can not find "memory" in hierachy level view.
 
>  
 
> the verilog simulator of mine is VCS in 
 workviewoffice
 
> 
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