Re: [openrisc] ORP and reset vector

["Sung-taek Lim" <stlim76@hotmail.com>]

Thank you, Maria and Marko for your answer.
It's clear now. But to think more about what Maria said,
though this might be off-topic, is there any solution other
than hard-wiring EPH to high? Can we distinguish power-on-
reset from hardware reset?

Regards,

Taek

>From: Marko Mlinar <markom@opencores.org>
>Reply-To: openrisc@opencores.org
>To: openrisc@opencores.org,   Marķa Bolado <mbolado@teisa.unican.es>
>Subject: Re: [openrisc] ORP and reset vector
>Date: Wed, 4 Dec 2002 08:19:09 +0100
>
>Hi!
>
>This is one way to do it. But even more ofter you have memory controller,
>there are several such on Opencores, that have power on configuration, 
>where
>you set where will your flash be (e.g. at 0x00000000), in boot code you
>reconfigure the MC and copy exception vectors to RAM e.g. at 0x00000000, 
>then
>start the OS. I believe uClinux does it this way.
>
>Marko
>
>On Tuesday 03 December 2002 16:44, Marķa Bolado wrote:
> > I guess that field EPH (Exception Prefix High) should be set by hardware
> > when a reset ocurrs, so that exception vectors are searched for in 
>memory
> > area starting at 0xF0000000. (Look page 27 in Architecture Manual).
> > Regards,
> >     Marķa Bolado
> >
> > ----- Original Message -----
> > From: "Sung-taek Lim" <stlim76@hotmail.com>
> > To: <openrisc@opencores.org>
> > Sent: Tuesday, December 03, 2002 9:08 AM
> > Subject: [openrisc] ORP and reset vector
> >
> > > Current ORP recommends mapping RAM to address 0x0.
> > > Then the reset vector at 0x100 belongs to RAM.
> > > How can I expect a valid instruction would exists
> > > there when I just turn the power on?
> > >
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