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The architecture cares only about the software
model and not how implementations implement these software model, as long as all
implementations are the same from software point of view. So the answer would be
that in case of FPU/VU, IC, DC, MMUs implementations can disable clock trees
when these units are not used, but for the CPU disbling the clock will
efectivelly freeze the execution of the program. So the CPU would only be gated
if:
- the CPU waits for example of IC, DC or any other
unit to complete its task in order for the CPU to continue (for example IC miss
would be an example)
- you want to freeze your system completetely until
and interrupt comes or a reset (this would be common for devices that are in
hibernate state)
As you see how CPU is de-gated is not important,
most likely it will be de-gated via interrupt controller. But this is
implementation specific.
regards,
Damjan
----- Original Message -----
Sent: Thursday, December 19, 2002 9:42
AM
Subject: [openrisc] Power Management
Unit
Hello, again!
I have seen that clock gating feature in Power
Management Unit 'utomatically
disables clock subtrees to major
processor internal units on a clock cycle basis. These blocks are usually the
CPU, FPU/VU, IC, DC, IMMU and DMMU. (...) Cache or MMU blocks
that are already disabled when software enables this feature, have completely
disabled clock subtrees until clock gating is disabled or until the blocks are
again enabled'.
In
the manual, you don't specify how the clock gating feature can be disabled
once it has been enabled. If CPU have no clock, I guess that it cannot be
done by writing in Power Management Register. I wonder if clock gating
feature is disabled by an external interrupt or by a reset, or whether
the architecture allows the implementation to choose how
control this feature.
Thank
you in advance
Marķa
Bolado
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