Re: [openrisc] OR1200 implementation of l.sb and l.sh

["Damjan Lampret" <lampret@opencores.org>]

>
> or1200 does not modify the whole word in cache, if it is l.sb or l.sh.
Cache
> is always
> coherent with main memory in or1200.
>
> regards,
> Damjan
>

BTW the simplest way to prove this is because there are four data cache RAM
cells, one RAM cell per byte (you can replace them by single RAM instance
with byte write enables if you ASIC memory compiler supports this).

regards,
Damjan


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