Re: [openrisc] OR1200 ASIC Success probabilities.

["Damjan Lampret" <lampret@opencores.org>]

Christian,

it all depends what kind of libraries you have. It has been implemented with
rather slow libraries (will not name any library vendors here) and post
layout timing was 120MHz in a SOC ASIC. But if you have fast libraries, in
particular memory cells, you can get a bit faster. Although 200MHz post
layout worst case will be hard. There have been some promising attempts to
design custom memories and optimize datapaths and they have reported to
expect to reach 200MHz worst case and there were some other attempts to go
beyond 200 in the range of 400MHz but that company closed so the project has
been terminated. Anyway your speed is very dependant on your libraries,
tools and experience, and of course what you will connect outside. At the
end I might want to mention that all outputs in OR1200 RTL are registered,
so critical paths could be either on inputs (they are not sampled) or inside
the OR1200 most likely around the register file if you use flop based
register file as opposed to hard macro memory based register file (in our
case of 120MHz we used flop based register file). Libraries, tools and
experince is most important for VDSM such as .18u or even more for .13u. So
if you don't have good VDSM flow don't attempt to get very high speeds using
VDSM geometry such as .18u.

regards,
Damjan

----- Original Message -----
From: "Christian Melki" <christian.melki@axis.com>
To: <openrisc@opencores.org>
Sent: Thursday, February 27, 2003 12:18 PM
Subject: [openrisc] OR1200 ASIC Success probabilities.


> Hello ppl.
>
> Im curious about the OR1200 ASIC synth success...
> Is there anybody out there who is successfully
> running the or1200 in 200MHz+ using a .18 6ML process
> of any kind?
> When I try to investigate where the or1200 will take me
> in synthesis by just hooking in the clock ( getting a probable
> direction tangent.. ) I get a bad slack by 1.4 on a 5ns clock
> input... 10ns is no problem of course.
> This is rather disturbing since the slack will probably
> only get worse when all the inputs and are connected and everything
> is defined correctly.. ( this is my guess. since more blocks will
> actually get synth:ed if everything is connected )
> The synthesis is done against a .18 lib using the same
> environment (configuration) that is very succesful for
> other (unnamed) large cores.
> Now im obviously no ASIC expert.. This is the first time
> ever i have synth:ed anything.. :) So any hints are
> greatly appreciated.
> Oh btw. Im using Build Gates for synthesis. :)
>
> best regards
> MScIT Stud.
> Christian Melki
> Sweden.
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