Re: [openrisc] Connect to JTAG, then?

["Damjan Lampret" <lampret@opencores.org>]

Heya !

1) You probably use generic memories (just a guess why it takes so much
time). Make sure you target it to Xilinx Virtex if you want to use Xess
XSV800 boards. Also on slow computer synthesis can take hours.
2) Console is available on RS232 port of XSV board. Connect a terminal to
RS232 port (you can use a PC with Hyper Terminal software).
3) There is a README file but chapter about synthesis is empty. I'll add
something in the future or you can add something if you will do
synthesis/implementation for XSV.

regards,
Damjan

----- Original Message -----
From: <reanphoto@yahoo.com.tw>
To: <openrisc@opencores.org>
Sent: Tuesday, April 29, 2003 5:13 AM
Subject: [openrisc] Connect to JTAG, then?


> Hi everyone,
>
> Thanks for the OpenRISC project, it's really a good project, well done.
>
> I am begin to try the xess version, I have some questions, please help
> me if somone know how to solve them, thanks
>
> 1. I try to synthesis the 'xsv_fpga_top.prj' by synplify pro 7.2.3, but it
> seems never end, always stay at 'compiling' stage, what's going on?
>
> 2. I load the 'xsv_fpga_top_ethernet.exo' into Flash memory, and
> connect the JTAG server through gdb, load the ORPmon, use the
> commands as the web page says, after command 'c', what should I do?
> how to display the ORPmon console?
>
> 3. Is there any document about synthesis, implementation hardware,
> then use some software tools to communication to the FPGA board step
> by step?
>
> thanks a lot.
>
> reanphoto
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