Re: [openrisc] cpu extensibility

[paul <paulw@mmail.ath.cx>]

Damjan Lampret wrote:

>Hi Paul,
>
>easy is a relative term. If you ask me, I'd say yes. The easiest way is to
>look how l.mul or l.mac are implemented.
>  
>
Can't find l.mul or l.mac. Only found "or1200_mult_mac.v". Looking at it 
right now.

I notice or1200 seem to be using device specfic RAM, like Xilinx's BRAM 
for register file or cache?
Why not use generic Verilog reg?

>regards,
>Damjan
>
>----- Original Message -----
>From: "paul" <paulw@mmail.ath.cx>
>To: <openrisc@opencores.org>
>Sent: Friday, June 06, 2003 1:34 PM
>Subject: [openrisc] cpu extensibility
>
>
>  
>
>>Hi
>>
>>Does the current OPENRISC structure (implementation), make adding new
>>instructions easy?
>>What I have in mind is to add instructions that can't be done in few
>>cycles but a lot of cycles.
>>Specifically, can I add a new instruction say -- that would do big
>>number multiplication , or do operations on a big chuck of memory, etc?
>>The C compiler don't have to know about the instructions, it will be
>>embedded assembly codes in C code.
>>Can it be done easily?
>>Thanks.
>>
>>
>>
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