Mail Index

• Thread Index

• Re: [openrisc] orp
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] Definitive source
  • From: "Damjan Lampret" <lampret@opencores.org>
• [openrisc] Old snapshot of gcc made available
  • From: Carlos Sánchez de La Lama <csanchez@teisa.unican.es>
• [openrisc] Definitive source
  • From: "Robert Cragie" <rcc@jennic.com>
• [openrisc] gcc errors
  • From: Carlos Sánchez de La Lama <csanchez@teisa.unican.es>
• Re: [openrisc] Cache Line Fill
  • From: Soban Shoeb Chawre <sobanc@nital.stpp.soft.net>
• Re: [openrisc] orp
  • From: "Damon Brantley" <brantley@mcloudteleco.com>
• RE: [openrisc] Cache Line Fill
  • From: "Michael Phan" <mphan@nimbuswireless.com>
• RE: [openrisc] Cache Modes In ORPsoc System
  • From: "Michael Phan" <mphan@nimbuswireless.com>
• Re: [openrisc] Cache Line Fill
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] Cache Modes In ORPsoc System
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] Cache Line Fill
  • From: mphan@nimbuswireless.com
• [openrisc] Cache Modes In ORPsoc System
  • From: mphan@nimbuswireless.com
• Re: [openrisc] orp
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] WB:RISC Clock Ratios
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: Re: [openrisc] WB:RISC Clock Ratios
  • From: "zhustudio" <zhustudio@ict.ac.cn>
• [openrisc] uClinux patches applied
  • From: Carlos Sánchez de La Lama <csanchez@teisa.unican.es>
• Re: [openrisc] WB:RISC Clock Ratios
  • From: Marko Mlinar <markom@opencores.org>
• Re: [openrisc] about cache scheme
  • From: Marko Mlinar <markom@opencores.org>
• [openrisc] about cache scheme
  • From: "zhustudio" <zhustudio@ict.ac.cn>
• Re: [openrisc] WB:RISC Clock Ratios
  • From: "zhustudio" <zhustudio@ict.ac.cn>
• [openrisc] WB:RISC Clock Ratios
  • From: "Brian Adams" <brian.adams@annapmicro.com>
• Re: [openrisc] Ethernet Core Performance
  • From: Matjaz Breskvar <phoenix@opencores.org>
• RE: [openrisc] Ethernet Core Performance
  • From: Michael@McAllisters.net
• Re: [openrisc] orp
  • From: Dries Driessens <ddr@denayer.wenk.be>
• Re: [openrisc] orp
  • From: Soban Shoeb Chawre <sobanc@nital.stpp.soft.net>
• Re: [openrisc] orp
  • From: paul <paulw@mmail.ath.cx>
• [openrisc] orp
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] is Cray needed to synthesize ORP
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] about WISHBONE
  • From: "Damjan Lampret" <lampret@opencores.org>
• [openrisc] about WISHBONE
  • From: "zhustudio" <zhustudio@ict.ac.cn>
• [openrisc] Use of test timing library?
  • From: Christian Melki <christian.melki@axis.com>
• Re: [openrisc] is there a way to rebuild or1ksim from verilog source
  • From: Marko Mlinar <markom@opencores.org>
• Re: [openrisc] about or1ksim and rtems
  • From: Marko Mlinar <markom@opencores.org>
• [openrisc] software multiplication
  • From: Matjaz Breskvar <phoenix@opencores.org>
• Re: [openrisc] is Cray needed to synthesize ORP
  • From: Christian Melki <christian.melki@axis.com>
• Re: [openrisc] is Cray needed to synthesize ORP
  • From: kevin@opencores.org
• [openrisc] or1200 compilation problem
  • From: paul <paulw@mmail.ath.cx>
• [openrisc] is Cray needed to synthesize ORP
  • From: paul <paulw@mmail.ath.cx>
• Re: [openrisc] Bug fixes for uClinux
  • From: Simon Srot <simons@opencores.org>
• Re: [openrisc] Bug fixes for uClinux
  • From: "Damjan Lampret" <lampret@opencores.org>
• [openrisc] Bug fixes for uClinux
  • From: Carlos Sánchez de La Lama <csanchez@teisa.unican.es>
• [openrisc] speed optimizations branch
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] How can i synthesize or1200?
  • From: kevin@opencores.org
• Re: [openrisc] How can i synthesize or1200?
  • From: hy kim <boina9456@hanafos.com>
• Re: [openrisc] How can i synthesize or1200?
  • From: kevin@opencores.org
• [openrisc] Ethernet Core Verification with dedicated testbench language
  • From: SUNGYON@aaww.com
• Re: [openrisc] How can i synthesize or1200?
  • From: =?EUC-KR?B?sejI8b/r?= <hykim@drlogic.co.kr>
• [openrisc] Is Flextronics' test chip of ORP compliant SoC OK?
  • From: =?gb2312?B?1cXTwA==?= <zhangyong@nari-china.com>
• Re: [openrisc] Re: openrisc-digest V1 #441
  • From: kevin@opencores.org
• Re: [openrisc] Re: openrisc-digest V1 #441
  • From: Patrick Pelgrims <patrick.pelgrims@pandora.be>
• [openrisc] Re: openrisc-digest V1 #441
  • From: paul <paulw@mmail.ath.cx>
• [openrisc] Thanks for the tip.
  • From: "Michael McAllister" <mmcallister@annapmicro.com>
• Re: [openrisc] Thanks for the tip.
  • From: "Jim Dempsey" <tapedisk@ameritech.net>
• Re: [openrisc] is there a way to rebuild or1ksim from verilog source
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] How can i synthesize or1200?
  • From: kevin@opencores.org
• Re: [openrisc] How can i synthesize or1200?
  • From: kevin@opencores.org
• [openrisc] about mips of or1200
  • From: "zhustudio" <zhustudio@ict.ac.cn>
• Re: [openrisc] How can i synthesize or1200?
  • From: hy kim <boina9456@hanafos.com>
• Re: [openrisc] Ethernet Core Performance
  • From: Simon Srot <simons@opencores.org>
• [openrisc] How can i synthesize or1200?
  • From: kevin@opencores.org
• Re: [openrisc] Thanks for the tip.
  • From: =?utf-8?B?5byg5rC4?= <zhangyong@nari-relays.com>
• [openrisc] Thanks for the tip.
  • From: "Michael McAllister" <mmcallister@annapmicro.com>
• RE: [openrisc] Ethernet Core Performance
  • From: "Igor Mohor\(opencores\)" <igorm@opencores.org>
• RE: [openrisc] Ethernet Core Performance
  • From: "Igor Mohor\(opencores\)" <igorm@opencores.org>
• [openrisc] Ethernet Core Performance
  • From: "Michael McAllister" <mmcallister@annapmicro.com>
• [openrisc] is there a way to rebuild or1ksim from verilog source
  • From: paul <paulw@mmail.ath.cx>
• Re: [openrisc] cvs or1ksim broken?
  • From: paul <paulw@mmail.ath.cx>
• Re: [openrisc] Bugs detected on or1ksim
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] cvs or1ksim broken?
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] Bugs detected on or1ksim
  • From: Carlos Sánchez de La Lama <csanchez@teisa.unican.es>
• [openrisc] cvs or1ksim broken?
  • From: paul <paulw@mmail.ath.cx>
• RE: [openrisc] Bugs detected on or1ksim
  • From: "Robert Cragie" <rcc@jennic.com>
• [openrisc] about or1ksim and rtems
  • From: paul <paulw@mmail.ath.cx>
• Re: [openrisc] Bugs detected on or1ksim
  • From: Scott Furman <sfurman@rosum.com>
• Re: [openrisc] I have to make suggestions.
  • From: paul <paulw@mmail.ath.cx>
• Re: [openrisc] OR1200 ASIC Success probabilities.
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] I have to make suggestions.
  • From: "Damjan Lampret" <lampret@opencores.org>
• [openrisc] I have to make suggestions.
  • From: paul <paulw@mmail.ath.cx>
• Re: [openrisc] setting the stall bit using GDB
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] Bugs detected on or1ksim
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] what is the target board for "orp"
  • From: "Damjan Lampret" <lampret@opencores.org>
• [openrisc] Date and Time !!
  • From: Patrick Pelgrims <patrick.pelgrims@pandora.be>
• Re: [openrisc] memory requirement for openrisc
  • From: Patrick Pelgrims <patrick.pelgrims@pandora.be>
• [openrisc] TTA architecture
  • From: paul <paulw@mmail.ath.cx>
• [openrisc] what is the target board for "orp"
  • From: paul <paulw@mmail.ath.cx>
• [openrisc] memory requirement for openrisc
  • From: paul <paulw@mmail.ath.cx>
• RE: [openrisc] may be some bug in making binutils under cygwin
  • From: "#KUGAN VIVEKANANDARAJAH#" <kugan@pmail.ntu.edu.sg>
• [openrisc] may be some bug in making binutils under cygwin
  • From: "zhustudio" <zhustudio@ict.ac.cn>
• Re: [openrisc] OR1200 ASIC Success probabilities.
  • From: Christian Melki <christian.melki@axis.com>
• Re: Re: [openrisc] Question About the MP3 decoding program, MINIMAD
  • From: "zhustudio" <zhustudio@ict.ac.cn>
• Re: [openrisc] setting the stall bit using GDB
  • From: Marko Mlinar <markom@opencores.org>
• Re: [openrisc] Question About the MP3 decoding program, MINIMAD
  • From: Marko Mlinar <markom@opencores.org>
• Re: [openrisc] about or1k
  • From: zhustudio@ict.ac.cn
• [openrisc] setting the stall bit using GDB
  • From: Michael@McAllisters.net
• Re: [openrisc] about or1k
  • From: Matjaz Breskvar <phoenix@fiz.uni-lj.si>
• Re: [openrisc] about or1k
  • From: "=?gb2312?B?1cXTwA==?=" <zhangyong@nari-relays.com>
• [openrisc] about or1k
  • From: zhustudio@ict.ac.cn
• Re: [openrisc] Question About the MP3 decoding program, MINIMAD
  • From: zhustudio@ict.ac.cn
• RE: [openrisc] Bugs detected on or1ksim
  • From: "Robert Cragie" <rcc@jennic.com>
• [openrisc] optimized OR1200 on Virtex II
  • From: "Martin Picha" <mpicha2@omnisky.net>
• Re: [openrisc] Bugs detected on or1ksim
  • From: Scott Furman <sfurman@rosum.com>
• Re: [openrisc] need help with boot strategy
  • From: Marko Mlinar <markom@opencores.org>
• Re: [openrisc] need help with boot strategy
  • From: Patrick Pelgrims <patrick.pelgrims@pandora.be>
• Re: [openrisc] need help with boot strategy
  • From: Marko Mlinar <markom@opencores.org>
• RE: [openrisc] need help with boot strategy
  • From: "Robert Cragie" <rcc@jennic.com>
• [openrisc] or32 linux port update
  • From: Matjaz Breskvar <phoenix@opencores.org>
• [openrisc] need help with boot strategy
  • From: paul <paulw@mmail.ath.cx>
• Re: [openrisc] Cache Line Fill
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] Cache Line Fill
  • From: mphan@nimbuswireless.com
• Re: [openrisc] Merging toolchain versions
  • From: Matjaz Breskvar <phoenix@opencores.org>
• Re: [openrisc] cpu extensibility
  • From: paul <paulw@mmail.ath.cx>
• RE: [openrisc] cpu extensibility
  • From: "Richard Herveille" <richard@asics.ws>
• Re: [openrisc] cpu extensibility
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] cpu extensibility
  • From: paul <paulw@mmail.ath.cx>
• Re: [openrisc] orp_soc compilation problem
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] orp_soc compilation problem
  • From: paul <paulw@mmail.ath.cx>
• Re: [openrisc] cpu extensibility
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] cpu extensibility
  • From: Marko Mlinar <markom@opencores.org>
• Re: [openrisc] cpu extensibility
  • From: paul <paulw@mmail.ath.cx>
• Re: [openrisc] Synplicity Synplify Pro on wine?
  • From: Shawn Tan <shawn.tan@aeste.net>
• Re: [openrisc] cpu extensibility
  • From: Marko Mlinar <markom@opencores.org>
• Re: [openrisc] Patch for correctiong timeout interrupt
  • From: Marko Mlinar <markom@opencores.org>
• [openrisc] Synplicity Synplify Pro on wine?
  • From: paul <paulw@mmail.ath.cx>
• [openrisc] cpu extensibility
  • From: paul <paulw@mmail.ath.cx>
• [openrisc] Patch for correctiong timeout interrupt
  • From: Carlos Sánchez de La Lama <csanchez@teisa.unican.es>
• [openrisc] Merging toolchain versions
  • From: Carlos Sánchez de La Lama <csanchez@teisa.unican.es>
• [openrisc] Merging toolchain versions
  • From: Carlos Sánchez de La Lama <csanchez@teisa.unican.es>
• Re: [openrisc] OR1200 ASIC Success probabilities.
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] orp_soc compilation problem
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] orp_soc compilation problem
  • From: paul <paulw@mmail.ath.cx>
• Re: [openrisc] orp_soc compilation problem
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] orp_soc compilation problem
  • From: paul <paulw@mmail.ath.cx>
• [openrisc] help about uclinux
  • From: Soban Shoeb Chawre <sobanc@nital.stpp.soft.net>
• Re: [openrisc] New SDK for OpenRISC 1000
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] Bugs detected on or1ksim
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] Bugs detected on or1ksim
  • From: Marko Mlinar <markom@opencores.org>
• Re: [openrisc] orp_soc compilation problem
  • From: "Damjan Lampret" <lampret@opencores.org>
• [openrisc] OR1200 ASIC Success probabilities.
  • From: Christian Melki <christian.melki@axis.com>
• Re: [openrisc] Bugs detected on or1ksim
  • From: Carlos Sánchez de La Lama <csanchez@teisa.unican.es>
• [openrisc] orp_soc compilation problem
  • From: paul <paulw@mmail.ath.cx>
• Re: [openrisc] New SDK for OpenRISC 1000
  • From: Matjaz Breskvar <phoenix@fiz.uni-lj.si>
• Re: FW: FW: [openrisc] GCC problem
  • From: Matjaz Breskvar <phoenix@opencores.org>
• Re: [openrisc] Bugs detected on or1ksim
  • From: Scott Furman <sfurman@rosum.com>
• Re: [openrisc] New SDK for OpenRISC 1000
  • From: Scott Furman <sfurman@rosum.com>
• Re: [openrisc] Bugs detected on or1ksim
  • From: Matjaz Breskvar <phoenix@opencores.org>
• Re: FW: FW: [openrisc] GCC problem
  • From: Matjaz Breskvar <phoenix@fiz.uni-lj.si>
• Re: FW: FW: [openrisc] GCC problem
  • From: "Damjan Lampret" <lampret@opencores.org>
• [openrisc] Bugs fixed in new version of gcc for OpenRISC
  • From: Carlos Sánchez de La Lama <csanchez@teisa.unican.es>
• Re: FW: FW: [openrisc] GCC problem
  • From: Carlos Sánchez de La Lama <csanchez@teisa.unican.es>
• [openrisc] Bugs detected on or1ksim
  • From: Carlos Sánchez de La Lama <csanchez@teisa.unican.es>
• FW: FW: [openrisc] GCC problem
  • From: "rchowdsl" <rchowdsl@pacbell.net>
• [openrisc] Undo, A Novel by Joe Hutsko and 3000 more...
  • From: "Dionne Mora" <floodedinvoluntsinned@posta.hu>
• Re: [openrisc] New SDK for OpenRISC 1000
  • From: Carlos Sánchez de La Lama <csanchez@teisa.unican.es>
• Re: [openrisc] New SDK for OpenRISC 1000
  • From: Marko Mlinar <markom@opencores.org>