Re: [openrisc] cpu extensibility

[paul <paulw@mmail.ath.cx>]

Hi

I guess this question is a bit besides the topic:
Has anyone experience with Xilinx's "easypath" solution?

Richard Herveille wrote:

>I guess what Paul's saying is that FPGA synthesis tools are capable of
>recognizing the memory construction and map this directly to FPGA memory
>blocks. This is true and it can be used, however only for FPGAs. If you
>want to move to an ASIC you need to instantiate the memory block
>explicitly.
>
>Richard
>
>
>-----Original Message-----
>From: owner-openrisc@opencores.org [mailto:owner-openrisc@opencores.org]
>On Behalf Of Damjan Lampret
>Sent: zaterdag 7 juni 2003 1:58
>To: openrisc@opencores.org
>Subject: Re: [openrisc] cpu extensibility
>
>
>Paul,
>
>l.mul, l.mac, l.msb are instructions. You can start with
>or1200_mult_mac.v and trace back how instructions control this unit.
>
>To answer your question about a verilog reg I'll say buy a good book on
>verilog and ASIC design. Specific RAMs are instantiated because this is
>how things have to be done, you can't have thousands of flip flops used
>as cache memories ... BTW Verilog reg is not a flip flop by definition -
>it is only a concept in verilog that you can use to construct a flip
>flop (or can it be a latch or often a non-sequential element as well
>!!).
>
>regards,
>Damjan
>
>----- Original Message -----
>From: "paul" <paulw@mmail.ath.cx>
>To: <openrisc@opencores.org>
>Sent: Friday, June 06, 2003 10:39 PM
>Subject: Re: [openrisc] cpu extensibility
>
>
>  
>
>>Damjan Lampret wrote:
>>
>>    
>>
>>>Hi Paul,
>>>
>>>easy is a relative term. If you ask me, I'd say yes. The easiest way 
>>>is
>>>      
>>>
>to
>  
>
>>>look how l.mul or l.mac are implemented.
>>>
>>>
>>>      
>>>
>>Can't find l.mul or l.mac. Only found "or1200_mult_mac.v". Looking at 
>>it right now.
>>
>>I notice or1200 seem to be using device specfic RAM, like Xilinx's 
>>BRAM for register file or cache? Why not use generic Verilog reg?
>>
>>    
>>
>>>regards,
>>>Damjan
>>>
>>>----- Original Message -----
>>>From: "paul" <paulw@mmail.ath.cx>
>>>To: <openrisc@opencores.org>
>>>Sent: Friday, June 06, 2003 1:34 PM
>>>Subject: [openrisc] cpu extensibility
>>>
>>>
>>>
>>>
>>>      
>>>
>>>>Hi
>>>>
>>>>Does the current OPENRISC structure (implementation), make adding 
>>>>new instructions easy? What I have in mind is to add instructions 
>>>>that can't be done in few cycles but a lot of cycles.
>>>>Specifically, can I add a new instruction say -- that would do big
>>>>number multiplication , or do operations on a big chuck of memory,
>>>>        
>>>>
>etc?
>  
>
>>>>The C compiler don't have to know about the instructions, it will be
>>>>embedded assembly codes in C code.
>>>>Can it be done easily?
>>>>Thanks.
>>>>
>>>>
>>>>
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>>>      
>>>
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