[openrisc] Cache Modes In ORPsoc System

[mphan@nimbuswireless.com]

Hi Damjan,

We are running into some problems when we implement the ORPsoc in 
Xilinx FPGA, we hope you can give us some hints to solve them.

Here is our configuration:
NO DATA MMU
NO INSTRUCTION MMU
NO DATA CACHE
WITH INSTRUCTION CACHE ( 4 KB)

But in the LAB we can only run the DC mode.
The other three did not run: NOCACHE, IC, and ICDC.

Have you seen this before.

Hope you can give us some answers

Thanks
Michael Phan
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