RE: [fpu] FPU operations

[Damjan Lampret <damjanlampret@yahoo.com>]

> compare instruction? so they will act as register from
> teh cpu point of view that will be read only after the
> comparison.

Not like registers. You assume CISC like machine. Actually there can be
several compare insns (not FPU operations!) that compare two operands.
So when FP compare is issued sets FPU operation to a particular kind of
compare and FPU sets status signals after fixed time of clk cycles. So
status flags can be registered but they are not like special purpose
registers. They are simply outputs from the FPU. Signals. CPU knows how
many clk cycles compare needs (of course it can be only one cycle if
possible). Anyway if compare speed depends upon operands then FPU
should provide handshaking like stall or something to stall CPU until
compare finishes. Relly much simpler then to have SPRs.

> 
> Damjan can OR1k handel different speeds of execution
> units? does teh FPU have to do any action regarding

Yes.

> that or should I assume that all instructions will be
> ordered properly that no contention will be on teh
> result interface?

Result buses from different units are muxed. No contention possible.
Anyway in high speed processors buses between functional units are not
tristate.

--damjan


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