RE: [fpu] FPU operations

[Damjan Lampret <damjanlampret@yahoo.com>]

> instructions will look at those status bits (as far as I know).
> The comparator will operate on operands A and B, so if I do
> an ADD of A and B, I don't care about 'larger then' or 'smaller
> then' or 'equal' flags. I can see that 'unordered' and 'infinity'
> might be useful, but even then, I don't see how and ADD instruction
> (for example) can use those status flags.

Actually if adding "compare" functionality to standard instructions is
not a performance penalty then we should do it. GCC can generate code
for this. It is just like CISC code for integer arithmetics. Same
applies for FP. So if it is possible to do compare right after result
is calculated (but for example not yet normalized or something) and
this doesn't affect perfomance then we should do it. This could speed
up things quite a bit. But only if this doesn't affect performance.

> One thing came to mind thou: A result==zero status flag *might* be
> useful, if there are 'increment and jump if zero' or 'decrement
> and jump if zero' (and whatever other variations one can come up
> with)
> are. The type of instructions are typical for integer operations, I'm
> not sure if they make sense for floating point ...
> 

Not just zero. All would be useful. Imagine in most cases you might not
even need compare insn in the code to do control (control == compare
and then do branch if condition true). You would only need to do
compare when you want to compare when status of operation is already
overwitten by following operation. You know what I am talking - just
like in most CISCs.

> No, again, this is something the CPU MUST do. All outputs might
> change every cycle, as the inputs change (however, pipelined).
> The CPU must track the results and status information. The FPU
> is nothing else as a pipelined calculation engine, it has no
> states.
> 
Exactly.

--damjan


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