Fw: [pci] PCI bridge status

["Tadej" <tadej@opencores.org>]

> Hi Ovidiu!
>
> That is OK.
> Do you have already anything done or are you starting at the moment.
> If you done anything (that would be great :), than we must adapt the
> interface to the FIFO.
> Miha and I ware thinking about interfaces, and
> we conclude, that the simplest way of BUS to BUS (not to configuration)
> interface, regardless bursts or single transfers, is through FIFO.
> It is simple to support more writes/reads  and beside that it is a good
way
> of different clock adapting.
> By the way, what do you think abaut address translation logic. I think,
> that for every image to WISHBONE bus exists its own address translation
> logic (as described in the spec). Thats why it shoud be a separate module,
> that we will be able to choose the number of images (2 - 5) when
> sinthesizing.
>
>
> regards, Tadej.
>
>
> -----Original Message-----
> From: owner-pci@opencores.org [mailto:owner-pci@opencores.org]On Behalf Of
> Ovidiu Lupas
> Sent: Wednesday, May 09, 2001 4:39 AM
> To: pci@opencores.org
> Subject: Re: [pci] PCI bridge status
>
>
> Hi all !
>
> I am interested in working on the PCI target interface.
>
> Best regards,
>    Ovidiu
>
>
> ----- Original Message -----
> From: Miha Dolenc <mihapci@email.si>
> To: <pci@opencores.org>
> Cc: <cores@opencores.org>
> Sent: Tuesday, May 08, 2001 10:17 AM
> Subject: [pci] PCI bridge status
>
>
> > Hello all!
> >
> >     I have updated the specification with some waveforms so it became
more
> > readable. We have also shrunken it to "only" 1.6MB.
> >
> > It can still be found on OpenCores CVS on address
> >
http://www.opencores.org/cgi-bin/cvsget.cgi/pci/docs/pci_specification.pdf
> >
> > Now I think there is quite enough information about PCI bridge core
> > functionality for us to start working on RTL design ;-) (in Verilog if
> > possible). I will think over how tasks can be divided. If anyone has any
> > idea about the task that must be done and he/she is interested in doing
> it,
> > please notify other members of PCI team through this mailing list, so we
> > don't do same things twice.
> >
> > I would like to do WISHBONE slave interface if nobody else is interested
> in
> > that.
> >
> > Have fun,
> >     Miha Dolenc
> >
>
>
>