Fw: [pci] PCI bridge status

["Tadej" <tadej@opencores.org>]

> Hi Tilen!
>
> I have some ideas abaut FIFO.
> I wrote to Ovidiu abaut adapting the PCI target interface to FIFO.
> The principles of interfacing FIFO to the PCI target should be the
> same as interfacing it to the WISHBONE slave interface.
> I will publish the new revision of spec soon (today or tomorow),
> where I described a litle bit more abaut FIFO architecture.
>
> And the idea is thet the FIFO can be (in FPGA architecture) a
> two-port RAM (somebody calls that non real dual-port RAM, etc.)
> with two separeted counters and a litle bit of logic. I ment with
> two-port RAM a RAM which consists of one WRITE (READ will
> not be used) port and the other just READ port. Boath ports
> have different clocks, since the clock frequncy of the reading port
> has no connection with clock connected to the memory register
> (which is writing clock frequncy).
>
> If you have any question, just post it to the mailing list.
>
> Regards, Tadej.
>
> -----Original Message-----
> From: owner-pci@opencores.org [mailto:owner-pci@opencores.org]On Behalf Of
> Tilen
> Sent: Wednesday, May 09, 2001 7:29 AM
> To: pci@opencores.org
> Subject: Re: [pci] PCI bridge status
>
>
> Hi!
>
> I read the spec, and I must say that it helped me to understand
> PCI wery good.
> I'm interested in working on FIFO.
>
> Regards, Tilen
>
> ----- Original Message -----
> From: "Ovidiu Lupas" <olupas@opencores.org>
> To: <pci@opencores.org>
> Sent: Wednesday, May 09, 2001 4:39 AM
> Subject: Re: [pci] PCI bridge status
>
>
> > Hi all !
> >
> > I am interested in working on the PCI target interface.
> >
> > Best regards,
> >    Ovidiu
> >
> >
> > ----- Original Message -----
> > From: Miha Dolenc <mihapci@email.si>
> > To: <pci@opencores.org>
> > Cc: <cores@opencores.org>
> > Sent: Tuesday, May 08, 2001 10:17 AM
> > Subject: [pci] PCI bridge status
> >
> >
> > > Hello all!
> > >
> > >     I have updated the specification with some waveforms so it became
> more
> > > readable. We have also shrunken it to "only" 1.6MB.
> > >
> > > It can still be found on OpenCores CVS on address
> > >
> http://www.opencores.org/cgi-bin/cvsget.cgi/pci/docs/pci_specification.pdf
> > >
> > > Now I think there is quite enough information about PCI bridge core
> > > functionality for us to start working on RTL design ;-) (in Verilog if
> > > possible). I will think over how tasks can be divided. If anyone has
any
> > > idea about the task that must be done and he/she is interested in
doing
> > it,
> > > please notify other members of PCI team through this mailing list, so
we
> > > don't do same things twice.
> > >
> > > I would like to do WISHBONE slave interface if nobody else is
interested
> > in
> > > that.
> > >
> > > Have fun,
> > >     Miha Dolenc
> > >
> >
> >
>
>
>