[pci] Config Space

[oliver.amft@ch.abb.com]

Tadej

Sorry, I should have read the papers more precisely.
Has there been any public discussion about this extended config space - I walked
through the mailing list history but couldn't find anything. So I ask my
question right away: Why are those configuration registers not in the PCI
configuration space? This would lead to the maximum config flexibility on PCI
side (1-6 possible base address registers).

Cheers,
Oliver




----- Original Message -----


Subject:  Re: [pci]  PCI IP core

Hi!

Yes, I actually mentioned the extended Config Space (I'm sorry, because
there is no clear reference to Device Specific Configuration registers - my
mistake). Registers in this space are all registers of the core (Device).
Yes, a part of this registers are also for image mapping, but there are also
registers for interrupts, error control and two special registers, which are
used for generating the configuration cycles on the PCI bus, but only when
core is configured as PCI host.

At this point, I must say, that there is SHORTER PDF specification (still
the
same revision) on the web, about 660 kB.

Regards, Tadej