Re: [pci] PCI core PROGRESS

["Mihaela & Ovidiu Lupas" <lupasfam@sympatico.ca>]

Hi !

I am working on the PCI target, and then I will do also PCI master
interface.
My problem is that I cannot commit to tigth deadlines, since I do not have
too
much time for this funny activities.

I am alost ready with the target device (I am porting it from my VHDL
version).
So, I will write incoming data directly to the FIFO, and I will signal
Address valid to
Tilen ?

I will send later today, my idea how to interface with the others. But, I
did not
finnished reading the specs yet ... ;)

Best regards,
  Ovidiu

----- Original Message -----
From: Tadej <tadej@opencores.org>
To: PCI <pci@opencores.org>
Sent: Thursday, May 24, 2001 7:23 AM
Subject: [pci] PCI core PROGRESS


Hi !

Miha is already verifying FIFO module, what will be somehow an interface (or
a major part of an interface) between PCI master/target and WISHBONE
slave/master.
Yesterday I meat Tilen and I gave him some advices about Verilog. Today I
think he is finishing an address decoder module (with address translation),
as described in spec.
Miha would like to do the WISHBONE slave module, when he will finish the
FIFO and I started with the WISHBONE master module.

So, if there is anybody interested to contribute to the PCI core (PCI
interface or a part of it, maybe verification, etc.), feel free to post your
message.
Whatever you contribute, will be used and all the guys that help in
development, specification or verification will appear as co-authors on
OpenCores webpage, if they want.

Regards, Tadej.