Re: [pci] a simple PCI target module

[ezhcai@ntu.edu.sg]

I suppose the data from back end applications are from synchronous RAM
(such as RAM blocks in Virtex/Spartan-II), which is synchronized before 
enter the PCI target.
pls let me know if my thinking is wrong.

Have a nice day,

Cai zhaohui

----- Original Message ----- 
From: sumnow <sumnow@2... > 
To: "pci@o... " <pci@o... > 
Date: Wed, 27 Mar 2002 17:0:39 +0800 
Subject: Re: [pci] a simple PCI target module 

> 
> 
> i think signals output to PCI bus should be 
> registered(synchronized) before they actually output to bus, which 
> can prevent glitch on PCI bus. and so do OE signals. 
> 
> synchronized signals can also benefit synthesis process. 
> 
> just some opinions and i am also not sure about it. 
> 
> >Hi there, 
> > 
> >A simple PCI revision 2.1 target module has been developed and 
> can be 
> >downloaded from 
> www.ntu.edu.sg/home/ezhcai/IPdesign/pcitarget.zip 
> > 
> >Any commets are very welcome. 
> > 
> >have a nice day, 
> > 
> >Cai zhaohui 
> > 
> 
--
To unsubscribe from pci mailing list please visit http://www.opencores.org/mailinglists.shtml