Re: [pci] why read is slower than write ?

["Miha Dolenc" <mihad@opencores.org>]

Hi!

I don't know what you mean exactly!  Are you talking about OpenCores pci
bridge? Master or Target?
If you are referring to why PCI Target has 1 initial wait cycle for reads
and none for writes, the reason is because outputs must be registered.
Target has to pull data out of FIFO and put it in output registers before
asserting TRDY.
Did this help?

Regards,
Miha Dolenc

----- Original Message -----
From: "Madhusudhan Rao" <madhu_sudhana_rao@yahoo.com>
To: <pci@opencores.org>
Sent: Wednesday, March 27, 2002 11:11 AM
Subject: [pci] why read is slower than write ?


> Hi,
>    When i am implementing pci memory read transactions
> i was in a need of keeping 2 wait cycles for proper
> read operation but for write with 1 clock cycle i am
> able to memory write. what may be the reason can any
> body give suggestions. All kinds of inputs are
> welcome.
>
> Thanks in advance
> Madhu
>
>
> =====
> MadhusudhanaRao.M
>
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