[pci] PCI Updated

["Miha Dolenc" <mihad@opencores.org>]

Hello all!

PCI Bridge project was just updated.
In short:
- PCI Base Address Mask register 5 had wrong reset value assigned
   (repaired and testcase added)

- Detected Parity Error bit in PCI Device Status register was set for all
kinds of
   parity errors, while it should be set only for Master Reads and Target
Writes
   (repaired the design and testbench to act as they should.)

- Added a few testcases - mostly for Configuration and Interrupt Acknowledge
  Cycle generation in HOST bridge.

Regards,
Miha Dolenc


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