When I tried to simulate the PCI core,the log file of VCS tell me that there are some parity errors occured. 1.Invalid write data parity error 2.Undetected read data parity error I want to know whether I am simulating the core in a wrong way. Any help will be appreciated! regards, wangc -- To unsubscribe from pci mailing list please visit http://www.opencores.org/mailinglists.shtml