Re: [pci] what is vs_hdtp_64x16???

[cfk <cfk@pacbell.net>]

Dear f4053:
    I suspect your problem is on of configuration in pci_user_constants.v.
Basically, there are some ifdef's for XILINX, FPGA, PCI_XILINX_RAMB4 and
others that affect the way that wb_tpram.v and pci_tpram.v synthesize. You
need to understand the library in ISE5.1 and its relationship with the
modules defined in the opencore project in order to make it work. I can tell
you that I have synthesized this in a Spartan II, Virtex and Virtex2Pro and
they all work.
    I can also tell you that I have pci_constants.v added to my ISE project
at the same level as TOP, that is just blow the definition of the chip,
which currently on this setup is xc2vp7-6ff896-XST Verilog. For yours, it
will probably be something like: xc2s15, but it does work. Look more closely
into your ISE setup and you should prevail.

Charles

----- Original Message -----
From: <f4053@hotmail.com>
To: <pci@opencores.org>
Sent: Friday, February 21, 2003 3:03 AM
Subject: [pci] what is vs_hdtp_64x16???


> Hello,
> I'm not so familiar with fpga's and the related tools but I try to
implement the pci core in the spartan II. I use the
insight-developmentboard.
> So here is my first problem:
>
> - I created a new project in ISE5.1
> - included top.v; then the subfiles appear (red highlighted)
> - after this I added the the other files, but under the file TPRAM.v there
>    is the file vs_hdtp_64x16 (no file extention)
> Can anybody tell me what this is and how I solve the problem?
>
> Another error occurs when I try to synthesize top.v. The error description
is: "could not include pci_constants.v".
> But I have added this file to the project. It appears not under the top.v
tree, but it is above top.v at the same level.
>
> Thanks in advance for your help.
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