Re: [openrisc] Unimplemented features in OR1200 Debug Unit

["Damjan Lampret" <lampret@opencores.org>]

Hi Anders,

these particular features you mention are not needed for debug. The two
particular output ports that you mnetioned are only used by trace and nobody
really implemented trace yet.

regards,
Damjan

----- Original Message ----- 
From: "Anders Nordstrom" <asic@sympatico.ca>
To: <openrisc@opencores.org>
Sent: Wednesday, August 13, 2003 7:39 PM
Subject: [openrisc] Unimplemented features in OR1200 Debug Unit


> Hi,
>
> Is anyone working on the or1200_du.v? I have been running Verilog
simulations
> and I noticed that the dbg_is_o output from the OR1200 never changed. I
looked
> at the Verilog code and it turns out that several features that are
documented in
> the OpenRISC 1200 IP Core Specification are not implemented in the RTL
code.
> For example; bit 1 of dbg_is_o is tied to zero and bits [2:0] of dbg_lss_o
are also
> tied to zero.
> How can you successfully run gdb if the debug unit is not fully
implemented? Are
> the missing pieces not used?
>
> Thanks,
>
>          Anders
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