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Re: [openrisc] Operating frequency after synthesis with ASIC lib.
Hi jinhyuk,
it is all what you said. First results with the Virtual Silicon libraries were always worse than with Artisan (especially memories). Second false paths are not listed yet, and they are there.
Additionally since last optimizations, the OR1200 went through some functional changes. During that periods the timing is not so important as is functional correctness of the core. Now it is going through final timing optimization. There are already some important timing optimizations, however they are not yet in the CVS.
Also DC and simulation scripts will soon be updated in the CVS as well.
regards,
Damjan
On 27 Mar 2002 04:54 CET you wrote:
> Hi, my name is jinhyuk
>
> I have downloaded the or1200 implementation - It looks cool!!.
> Thanks the works.
>
> My question is about achievable operating freq. of or1200 for ASIC implementation.
> The document says it operates at 250Mhz for 0.18um UMC/Virtual silicon lib., worst-case, post-layout.
>
> I sythesized or1200 with samsung 0.25um.
> I expected that the synthesized or1200 can operate at least 150Mhz worst-case, pre-layout.
> But, according to STA report, the maximum frequecy is about 100Mhz - big gap!!
> I can't understand what makes the biggg difference.
>
> It may be caused by library performance (speed).
> How about the performance of virtual silicon library?
> Is it better than other standard cell libraries? For example, Artisan library.
> Samsung lib. has almost same performance as Artisan library.
>
> Are there any false paths or multi-cycle paths in or1200 design?
> There's no disable timing commands in synthesis scripts included in or1200 distribution.
>
> Any suggestions or comments will be very halpful for me.
> Thank you in advance.
>
> /Jinhyuk Yang
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