Re: [oc] Memory synthesis

[Rudolf Usselmann <rudi@asics.ws>]

On Saturday 13 July 2002 08:27 pm, jae lim wrote:
> Hello everyone
>
> I am Jay and I am working on design a simple RISC
> pipeline processor. I am using Ncverilog for my
> verilog simulator and Design Compiler for my sythesis
> tool. My questions are:
>
> 1). What should I do with Data and Instruction Memory?
> For the simulation level, it is not hard, but after
> simulation, how can I synthesis the functional block
> with the memory?
>
> 2). Does anyone know what Mempro and SmartModel
> for?(they are synopsys memory product) and also, how
> to use them?

Try to use the generic memory models Damjan and friends wrote.
They represent real live memories in various technologies. You
probably want to refer to L1 cashes as SRAM blocks ?!

Decide on your memory/cache interface and then chose the
proper memories.

> Thank your guys forever...
>
> Jay

Regards,
rudi



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