[oc] Memory synthesis

[jae lim <jlim0011@yahoo.com>]

Hello everyone

I am Jay and I am working on design a simple RISC
pipeline processor. I am using Ncverilog for my
verilog simulator and Design Compiler for my sythesis
tool. My questions are:

1). What should I do with Data and Instruction Memory?
For the simulation level, it is not hard, but after
simulation, how can I synthesis the functional block
with the memory?

2). Does anyone know what Mempro and SmartModel
for?(they are synopsys memory product) and also, how
to use them?

Thank your guys forever...

Jay

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