Re: [oc] Memory synthesis

[John Sheahan <jrsheahan@optushome.com.au>]

On Sat, Jul 13, 2002 at 06:27:32AM -0700, jae lim wrote:
> Hello everyone
> 
> I am Jay and I am working on design a simple RISC
> pipeline processor. I am using Ncverilog for my
> verilog simulator and Design Compiler for my sythesis
> tool. My questions are:
> 
> 1). What should I do with Data and Instruction Memory?
> For the simulation level, it is not hard, but after
> simulation, how can I synthesis the functional block
> with the memory?

I think the answer depends on the memory size and target 
technology.   small memories (less than say few K bits) 
usually may as well be left to the synthesis tool.

bigger memories will benefit from a technology-specific 
custom layout,  either from the silicon vendor of one of 
the memory compiler folk.   

FPGA targets obviously have a different answer.
john
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