[oc] verilog to vhdl converter

[John Sheahan <jrsheahan@optushome.com.au>]

Hi

I recently wrote a perl script for converting synthesizeable 
verilog to vhdl.

It copes with most of the structures I use, but is bound to 
suffer when other styles are involved.

Is there any interst is posting and assisting tweaking this?
I'd like fragments of code it has trouble with, and the expected 
result (both if it works, and does not, for regression)

john
--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml