Re: [oc] verilog to vhdl converter

[Rudolf Usselmann <rudi@asics.ws>]

I think we should create a new section at OC for
tools. Recently somebody has submitted "perilog",
which supposed to be some sort of a tool as well.

Verilog to VHDL and VHDL to Verilog translators
are alway asked for. I think you should definitely
create a project page and submit your work to OC.

Damjan & Miha, can we create a new sub-category
for FREE tools ?

Regards,
rudi


On Fri, 2003-04-04 at 17:15, John Sheahan wrote:
> Hi
> 
> I recently wrote a perl script for converting synthesizeable 
> verilog to vhdl.
> 
> It copes with most of the structures I use, but is bound to 
> suffer when other styles are involved.
> 
> Is there any interst is posting and assisting tweaking this?
> I'd like fragments of code it has trouble with, and the expected 
> result (both if it works, and does not, for regression)
> 
> john
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rudi
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