Re: [oc] async/sync reset.

[John Sheahan <jrsheahan@optushome.com.au>]

On Thu, Apr 10, 2003 at 01:30:07PM +0200, cyrano@nerim.net wrote:
> Rudolf Usselmann <rudi@asics.ws> a �crit :
> 
> > On Thu, 2003-04-10 at 07:20, nico wrote:
> > > In most design guides, reset must be asynchronous to avoid hasard at
> > 
> > Oh really ?!  What hazard would that be ?
> > 
> 
> Mostly, the behavior of the output of the chip, during the power up and the beginning of the clock.


Also if the chip still uses tristate busses internally, driven 
from state machines ,  its possible to randomly generate nasty conflicts.

john
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