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Hi.
I have recently been tasked by my senior project advisor to write a 32-bit full adder and send the data out through the serial port in Verilog using the Digilent D2E (http://www.digilentinc.com) board which has the Xilinx Spartan IIE FPGA. This board already comes with a serial port and voltage level converter chip; however, it does not come with an UART controller. The manufacturer informs me that the UART controller is available from Xilinx, so I downloaded it from ftp://ftp.xilinx.com/pub/applications/xapp/xapp223.zip. This controller is actually a netlist that contains two EDIF files, UART_TX.EDN and UART_RX.END. The datasheet at http://www.xilinx.com/xapp/xapp223.pdf says to “Create Macro Symbol from Netlist.” My question is this: How do I take these EDIF files and actually turn it into macro? I don’t know where in Xilinx’s ISE Webpack 5.1 this option is as well as how to add these two files—if even necessary—to my project. Many thanks.
Benson
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