Re: [oc] How Do I Make UART EDIFs in Macros for Use in Projects?

[Armando Astarloa <jtpascua@bi.ehu.es>]

If those EDIF files have been created (by the vendor) using Xilinx
resources what you only have to do is the declaration and the
instantation of the edif black box into your code. For example, to use
the edif description of the kcpsm microcontroles (kcpsm.edn) the
declaration and instantiation in VHDL are as follow  (kcpsm.edn must be
into the working directory):

(declaration)
--
-- COMPONENT : KCPSM MICRO PICOBLAZE
--
component kcpsm is

        

        

Port
(

        

        

        

        

addr:

   

out
std_logic_vector(7 downto 0);

        

        

        

        

i:

      

in 
std_logic_vector(15 downto 0);

        

        

       

        

input: in  std_logic_vector(7 downto 0);

        

        

        

       

output: out std_logic_vector(7 downto 0);

        

        

        

        

port_id: out std_logic_vector(7 downto 0);

        

      

        

        

read_strobe: out std_logic;

        

        

        

        

write_strobe: out std_logic;

        

        

        

        

interrupt: in std_logic;

        

        

        

        

clk: in std_logic

        

        

        

        

);
end component;
(instantation)

--
-- KCPSM INSTANTATION
--
micro:kcpsm port map (

        

        

        

        

addr => ADDRESS_BUS,

        

        

        

        

i => INSTRUCTIONS_BUS,

        

        

        

       

input => INPUTS_BUS,

        

        

        

       

output => OUTPUTS_BUS,

        

        

        

        

port_id => PORTS_ID,

        

      

        

        

read_strobe => READ_STROBE,

        

        

        

        

write_strobe => WRITE_STROBE,

        

        

        

        

interrupt => INTERRUPT,

        

        

        

        

clk => CLK_I);


But, if you want to simulate an VHDL model (only for simluation and no for implementation pourposes) 
can be obteined from the edn file using Xilinx tool. First the edn must be translated to ngd (specifing
what will be the target) vand after that translated to VHDL. Here you have and example of the process
with the kcpsm.edn to kcpsm.vhd (On Spartan-II device):

ngdbuild -p xc2s150-5-pq208 kcpsm
ngd2vhdl -w kcpsm.ngd

Armando


At 13:21 10/04/2003 -0700, you wrote:

> Hi.
>
>  
>
> I have recently been tasked by my senior project advisor to write a 32-bit full adder and send the data out through the serial port in Verilog using the Digilent D2E (http://www.digilentinc.com) board which has the Xilinx Spartan IIE FPGA.  This board already comes with a serial port and voltage level converter chip; however, it does not come with an UART controller.  The manufacturer informs me that the UART controller is available from Xilinx, so I downloaded it from ftp://ftp.xilinx.com/pub/applications/xapp/xapp223.zip.  This controller is actually a netlist that contains two EDIF files, UART_TX.EDN and UART_RX.END.  The datasheet at http://www.xilinx.com/xapp/xapp223.pdf says to Create Macro Symbol from Netlist.   My question is this: How do I take these EDIF files and actually turn it into macro?  I don t know where in Xilinx s ISE Webpack 5.1 this option is as well as how to add these two files if even necessary to my project.  Many thanks.
>
>  
>
> Benson
>
>

----------------------------------------------------------------------------------------------------------------------
Armando Astarloa Cuéllar - Universidad del Pais Vasco UPV/EHU
Tecnología Electrónica
Departamento de Electrónica y Telecomunicaciones
Escuela Superior de Ingenieros - Email: jtpascua@bi.ehu.es
Ald. de Urquijo s/n Tel.: 34 - 94 - 601 73 04
48013 BILBAO (SPAIN) Fax.: 34 - 94 - 601 42 59
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