Re: [oc] async/sync reset.

[manxi wang <wangmanxi@yahoo.com>]

 well
--- cyrano@nerim.net wrote: > Joachim Strömbergson
> <Joachim.Strombergson@InformAsic.com> a écrit :
> 
> > Aloha!
> > 
> > cyrano@nerim.net
> > wrote:
> > > :) Funny. It's seems that it is another
> religious war. In the lab where i
> > work, sync reset are forbiden.
> > 
> > Yes it most certainly is. A war that just recently
> erupted, see:
> > 
> > http://www.deepchip.com/items/0396-01.html
> > http://www.eetimes.com/story/OEG20030401S0052
> > 
> > Rudis reference to Cliff Cummings paper is a good
> suggestion.
> > 
> > The trend for high-end VDSM-technologies (90nm and
> downwards) seems to be 
> > towards synch resets.
> > 
> 
> One things is bizard : sync reset could make meta
> stability, because you can't say that the release or
> the setting of the reset will not happen at edge of
> the clock. In case of async reset, i can't imagine
> than a metastability could arrive at release because
> all state are stable waiting for the next clock edge
> (between reset and release of reset, no signal
> change, so no glitch appear when the clock egde
> arrive).
> 
> Nicolas Boulay
> 
> > -- 
> > Med vänlig hälsning, Yours
> > 
> > Joachim Strömbergson - Alltid i harmonisk
> svängning.
> > VP, Research & Development
> >
>
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