RE: [oc] UART16550 core and 10/100 Base-T Core

["Ho, Wen Jei x4297" <who1@rockwellcollins.com>]

Since quite a few people are requesting for it, so her you go.
Don't ask for testbench, it is company confidential. ; - )

Wen

 

		-----Original Message-----
		From: owner-cores@opencores.org@ROCKWELLCOLLINS On Behalf Of
"Ho, Wen Jei x4297" <who1@rockwellcollins.com>
		Sent: Thursday, April 24, 2003 8:52 AM
		To: 'cores@opencores.org'
		Subject: RE: [oc] UART16550 core and 10/100 Base-T Core

		I also manually translated Ethernet (10/100 Base-T) Core
from Verilog to
		VHDL, and running well in simulation. Do you want it?

		Wen

		-----Original Message-----
		From: owner-cores@opencores.org@ROCKWELLCOLLINS On Behalf Of
		"Igor Mohor\(opencores\)" <igorm@opencores.org>
		Sent: Thursday, April 24, 2003 6:46 AM
		To: cores@opencores.org
		Subject: RE: [oc] UART16550 core

		Great.

		You can either send it to me (I'll put it to opencores for
		you) or add it to
		the cvs repository yourself.


		Regards,
		Igor

		-----Original Message-----
		From: owner-cores@opencores.org
		[mailto:owner-cores@opencores.org] On Behalf
		Of Ho, Wen Jei x4297
		Sent: Thursday, April 24, 2003 3:19 PM
		To: 'cores@opencores.org'
		Subject: RE: [oc] UART16550 core

		I manually translated the Verilog UART code from OpenCore to
		VHDL.
		It is running well in simulation. I was planning to send it
		back to the
		OpenCore society after tested in the Lab in the near future.

		If you want, I can send it to you now. However, I can't send
		test bench.

		Wen

		-----Original Message-----
		From: owner-cores@opencores.org@ROCKWELLCOLLINS On Behalf Of
		khchang@haco.co.kr
		Sent: Thursday, April 24, 2003 4:32 AM
		To: cores@opencores.org
		Subject: Re: [oc] UART16550 core



		----- Original Message -----
		From: ddresdner@p...
		To: carl@o... , cores@o...
		Date: Mon, 30 Sep 2002 23:33:16 -0100
		Subject: Re: [oc] UART16550 core

		>
		>
		> Igor,
		>
		> I would very much like to get a copy of your VHDL version
		of the
		> 16550
		> Uart. We would like to use it in a project that we are
		working on.
		> Would
		> it be possible to get the source for that. I would
		appreciated it.
		>
		> Thank you,
		> Danny Dresdner
		>
		> ddresdner@p...
		>
		> ----- Original Message -----
		> From: "Carl van Schaik" <carl@o... >
		> To: <cores@o... >
		> Date: Tue, 7 Aug 2001 08:04:19 +0200
		> Subject: Re: [oc] UART16550 core
		>
		> >
		> >
		> > Hi Igor,
		> >
		> > > so if I understand correctly, there are two versions,
		one
		> in
		> > Verilog that
		> > > was downloaded
		> > > from the opencores and one in VHDL that you wrote
		> (perhaps
		> > opencores files
		> > > translated to
		> > > VHDL and than changed).
		> > This is correct except that the Verilog was not simply
		> converted to
		> > VHDL.
		> > I have written UART's before and used the Verilog code
		mainly
		> as an
		> > example
		> > for my own code for the 16550.
		> >
		> > > I don't know which ones to take for testing. I'm a
		> verilog
		> > guy, not VHDL,
		> > > although I would
		> > > take the VHDL files if they contain less bugs than the
		> ones in
		> > verilog.
		> >
		> > Well, from what I saw, the Verilog version has a few
		bugs. The
		> main
		> > ones I
		> > noticed are:
		> >
		> > FIFO - not cleared when data is popped out(empty). -
		Error
		> bits
		> > could remain
		> > Break detection looked a bit weird (but I'm not a
		Verilog
		> person)
		> > Stop_bits signal in LCR(Line control register) is not
		used.
		> > Only 16550 mode is supported, not 16540.
		> > Break error is not passed through the FIFO!
		> > Reciever will continue to recieve (0's) after a break is
		> detected.
		> >
		> > > Can you tell me if I'm correct about the differences.
		> > >
		> > > In the meantime I'll start with the Verilog files.
		> > >
		> > > Regards,
		> > > Igor
		> >
		> > regards
		> > Carl
		> >
		>
		--
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