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Re: [oc] Async reset: active high or active low?

To: <cores@opencores.org>
Subject: Re: [oc] Async reset: active high or active low?
From: <cyrano@nerim.net>
Date: Mon, 28 Apr 2003 17:24:40 CEST
Reply-To: cores@opencores.org
Sender: owner-cores@opencores.org

I really ask why active low reset is used in our labs. It was answer that it is an historical raison because in TTL high level signal consumme less energy than low one. Power up is not concerne any more because logic begin to work at ~2.5 V.


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Webmail Nerim, http://www.nerim.net/


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Follow-Ups:
- Re: [oc] Async reset: active high or active low?
  - From: John Sheahan <jrsheahan@optushome.com.au>
- Re: [oc] Async reset: active high or active low?
  - From: Rudolf Usselmann <rudi@asics.ws>

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